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Driver Cho Gamepad Nazar V37.epub1. Field of the Invention
The present invention relates generally to a master slice integrated circuit and, more particularly, to a master slice integrated circuit having a redundancy circuit.
2. Description of the Background Art
Recent demands for a larger capacity semiconductor memory device lead to a need for an increased number of pins for the master slice integrated circuit to be mounted on a semiconductor chip. The increased number of pins inevitably causes a decrease in yield in the fabrication of the master slice integrated circuit. In order to avoid such a decrease in yield, it is necessary to increase the number of pins for the master slice integrated circuit.
One method of increasing the number of pins is to form a redundancy circuit for replacing a defective memory cell. The redundancy circuit is configured in accordance with the location of the defective memory cell to be replaced, and in accordance with the number of pins that are needed. For example, where the position of the defective memory cell to be replaced is determined as an outside area of a mask, the redundancy circuit is incorporated on the inside of the mask, thereby increasing the number of pins.
FIG. 5 is a schematic plan view showing an example of a master slice integrated circuit having a conventional redundancy circuit.
Referring to FIG. 5, a redundancy circuit 12 is provided on an inner side of a quadrangular region 11 of a semiconductor chip. The redundancy circuit 12 is comprised of memory cells 13 for storing redundancy address data, and an address decoder 15 for selecting either of the redundancy cells 13 to enable access to a memory cell array 14.
A decoder circuit 13b for decoding an address signal A0 (for example, an input signal from a row decoder) is provided in the memory cell 13. An address decoder circuit 15a decodes the redundancy address data, and outputs a redundancy enable signal.phi.R to the redundancy circuit 12. The address decoder circuit 15a is supplied with the redundancy address data from the memory cell 13 that is selected by the address decoder circuit 15. The address decoder circuit 15a includes a decoding circuit 15a0 which compares the address signal A0 (for example, the input signal from the row decoder) with a redundancy address data.
The redundancy circuit 12 includes a block of memory cells

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